The physics is real — and the claims are not interchangeable, because a simulation, a measured link, an evaluation kit and a signed joint venture all arrive in the press looking like the same kind of news. By Nicholas Thomas Monday, September 21, 2026 · Feature · Packaging, optics and the interconnect bottleneck The most interesting cable in artificial intelligence was borrowed from a device used to look inside the human body. Microsoft’s MOSAIC takes multicore imaging fibre — the kind mass-produced for endoscopy, carrying up to ten thousand cores in a single strand — and instead of sending a picture down it, sends hundreds of parallel data channels.
The company’s own paper is blunt about the provenance: imaging fibres “are mass-produced and commercially available for medical applications (e.g., endoscopy).” A component built to show a surgeon a stomach lining is being repurposed to move tokens between accelerators. Elsewhere, engineers are putting glass underneath processors, and another group of optical researchers is improving fibre by taking the glass out of the light’s path. Put those together, and the story is not that glass replaces copper.
It is that the industry has started attacking the distances, the materials and the interfaces sitting between computing capacity and useful work — and that some of the next real gains in AI infrastructure will come from making the system around the transistor less wasteful rather than making the transistor smaller. The desk’s interest here is narrower than the enthusiasm. Every claim below is sorted into one of four buckets: a signed agreement, a measured result, a vendor estimate, or a projection.
They are not the same thing, and the gap between them is where money is lost. Glass packaging is not one technology A terminology problem sits underneath most of the excitement. A glass carrier is temporary support used during manufacturing and thrown away.
A glass core stays inside the finished substrate. A glass interposer is an intermediate interconnection structure. Those are three different products with three different economics, and a photograph of chips being processed on glass establishes none of them.
Nor does glass mean a copper-free package. A glass-core architecture still carries copper wiring, metallised through-glass vias and polymer build-up layers. Intel’s own ECTC 2026 material, published on 2 June, describes glass-core substrates alongside embedded silicon bridges, fully copper-filled through-glass vias, and co-packaged optics — a system, not a sheet of glass standing in for a package.
Intel’s original disclosure, on 18 September 2023, is worth quoting properly because it is routinely quoted loosely. Intel claimed the “dimensional stability needed for extremely tight layer-to-layer interconnect overlay,” “ultra-low flatness for improved depth of focus for lithography,” and that “a 10x increase in interconnect density is possible on glass substrates.” Its timing language was “second half of this decade” — not a promise that accelerators migrate next year. Glass is also not automatically an optical network.
A transparent core supplies no emitter, no detector, no waveguide, and no aligned connector. And co-packaged optics can shorten an electrical path without any glass core. These technologies can reinforce one another.
They are not a bundle. Stable does not mean cool Here is the thermal surprise: a substrate can resist distortion under heat while being poor at carrying heat away. AGC’s published figure for its packaging glass is 0.8 watts per meter-kelvin — and it appears on the company’s marketing pages, not a datasheet, with no independent corroboration this desk could find.
Silicon is two orders of magnitude higher. That is a material property and not a demonstration that a finished glass package runs cooler. Even expansion matching is a compromise rather than an optimization.
AGC describes glass “with a controllable CTE that can be finely tuned to suit a particular packaging process,” spanning 3.3 to 12.0 parts per million per degree, and deliberately raises the coefficient for resin-heavy fan-out processes. The lowest expansion isn’t automatically the best. Why that matters at scale is arithmetic.
Take an illustrative 80-millimeter structure, a mismatch of 10 parts per million per degree, and a 200-degree excursion: the unconstrained difference in expansion is 160 micrometers. That is this desk’s arithmetic on invented inputs, not a prediction of bow or cracking in any real package — actual stress depends on thickness, geometry and constraint. It is printed to show why a dimension that sounds microscopic becomes structural across a large assembly.
The engineering task is not matching glass to silicon. It is making silicon, copper, glass, polymer and board tolerate one another. The hardest part is the inside of a hole Through-glass vias are the electrical paths through the substrate, and opening the hole is the easy part.
The inner wall must accept a conductive layer, the metal must fill without unacceptable voids, and the structure must survive assembly and repeated thermal cycling. On 1 September 2026, TRUMPF promoted high-power impulse magnetron sputtering as a way to coat inside deep, narrow glass features, using electric and magnetic fields to drive ionised material into places conventional deposition struggles to reach. That is a vendor claim relayed through trade press, with no published aspect-ratio figure and no customer yield to back it up.
And a correction to the language that circulates around glass-core cracking. SeWaRe is not an acronym and does not stand for anything. It is the Japanese 背割れ—wood-splitting—the name Koizumi gave to a horizontal crack that originates at the diced edge of a glass core after build-up layers form.
The stress comes from the expansion mismatch between glass and those build-up layers; singulation and thermal cycling are among the events that release it. A recent paper revisiting this is an ECTC 2025 paper by Wei and Frederick, who appear to be at Disco, the dicing-equipment maker, and the mitigation they describe is a pull-back method that removes laminated layers at the singulation edge. Preventing damage while making a via does not establish that the finished package survives a decade.
The economics get unforgiving as the count of critical features rises. Assume a million independent, indispensable connections, each with a one-in-a-million chance of failing. The probability that all survive is 36.8 percent.
That is this desk’s arithmetic on invented inputs — it assumes independence, no redundancy, and that every connection matters, none of which describes a real design. It is printed because it shows how an impressive per-feature success rate can still produce an unsellable system yield. Durable value in this layer is more likely to accumulate around cleaning, coating, inspection, stress management, and qualification than around supplying square meters of glass.
When the display stops showing pictures The counterintuitive idea in MicroLED interconnect is not that an LED beats a laser. It is that the system may not need any individual channel to be fast. Microsoft calls it a wide-and-slow architecture, and the paper’s own example is a 20-by-20 array at 2 gigabits per channel—400 channels, 800 gigabits aggregate—in a die under a millimeter square.
That is a design calculation in Microsoft’s paper, not a module that has passed qualification. The measured boundary is more specific and more useful. The MOSAIC paper — ACM SIGCOMM 2025, Coimbra, and the conference’s best paper — reports a 100-channel prototype measured 25 channels at a time, sustaining 2 gigabits per channel over 20 meters below the error threshold.
At 30 meters, the error rate exceeded that threshold at 2 gigabits, and the rate was cut to 1.6. The 50-meter pluggable module is a simulation: “simulations indicate that the pluggable module should sustain 2 Gbps transmission over 50 m.” Built, measured, projected — three different words, and the paper uses them correctly even where the coverage does not. A second saving hides in the architecture and has nothing to do with light.
The paper proposes forwarding the transmitter’s clock down a dedicated channel so each receiver can use it directly, “without a power-hungry CDR.” In a link with hundreds of channels, spending one on timing is cheap. The efficiency comes from not building the fast electronics that make a very fast lane behave. On 17 March 2026, MediaTek described the integrated version with Microsoft: a single custom monolithic CMOS chip carrying the electronics, with MicroLED and photodetector arrays bonded directly onto it, scaling “to 800 Gbps and beyond within standard QSFP/OSFP form factors.” Microsoft puts commercialisation with partners in late 2027 and estimates about 50 per cent less energy than mainstream laser-based optical cables, on its own lab tests.
That 50 per cent deserves a footnote the coverage rarely gives it. The SIGCOMM paper claims more — 3.1 to 5.3 watts for the optical link, “56–68% lower than mainstream baseline.” Fifty per cent is the conservative, productised number from Microsoft’s newsroom and MediaTek. It compares cables, originates with the companies selling them, and is emphatically not a claim that an AI campus draws half the power.
The connector decides whether it leaves the lab A cable that works on a bench is not a cable a technician can install, diagnose and replace at three in the morning. Avicena shipped 1-terabit LightBundle evaluation kits in August 2026 — a 335-channel MicroLED array, each channel running up to 3 gigabits. Evaluation hardware is real, and it is not an accelerator adopting the technology.
On 17 September, the company announced a connectorised demonstration for the ECOC exhibition in Málaga, 21 to 23 September, using “an industry-standard MPO form factor combined with a ferrule optimized for multi-core fiber bundles.” A familiar mechanical shell helps integration. It does not make the thing optically compatible with the MPO plant already installed. MicroLED is not alone in facing this.
Co-packaged optics moves the optical engine next to the switch die, but the lasers can stay outside — and NVIDIA is unusually candid about why. Its silicon-photonics architecture puts lasers “on front-panel external laser source pluggable OSFP modules, enabling quick diagnosis and replacement while the switch core remains sealed,” describing them as “the most failure-prone components.” Its XDR switch documentation carries a replacement procedure for those modules. An industry used to pulling a front-panel module will not judge this on energy per bit.
It will judge it on downtime, repair labour and the value of the equipment a failure puts at risk. The winning optical design has to survive a maintenance schedule. Sometimes the improvement is less glass At distance, the material story inverts.
Hollow-core fibre keeps a structured glass boundary but runs most of the light through air. A Nature Photonics paper published on 1 September 2025 reported “measured loss of 0.091 dB km⁻¹ at 1,550 nm that remains below 0.2 dB km⁻¹ over a window of 66 THz” — the work of the Optoelectronics Research Centre at Southampton with Microsoft’s Azure Fibre operation — a research result on a tested fibre, not a guarantee for an installed cable plant. The speed claim needs to be handled with tongs.
Microsoft’s Azure blog says: “As light travels faster through air than glass, HCF is 47% faster than standard silica glass.” That is propagation velocity in the medium. It is not 47 per cent more line rate, not 47 per cent more tokens, not a training run 47 per cent shorter — and Tom’s Hardware’s rendering of it as “47% faster data transmission” is the error this desk would log. Coverage of the Nature paper itself carries 45 per cent rather than 47; the two numbers come from different places and should not be merged.
A 47 per cent gain in propagation speed cuts propagation time by 32 per cent, not 47 per cent. Concretely: light in silica at a refractive index near 1.468 takes about 4.90 microseconds per kilometre, and an air path about 3.34. Over 100 kilometres, that is roughly 490 microseconds against 334.
Desk arithmetic, inputs printed, isolating the medium — real links add switching, transceivers and routing. Lower propagation delay widens the map of sites that fit inside a network budget, which matters when the binding constraint is power availability. But a network budget is not only a propagation budget, and fibre latency does not resolve a grid connection or a planning objection.
Manufacturing is following the physics. Corning announced on 23 September 2025 that its North Carolina plants would produce Microsoft’s hollow-core fibre, with the collaboration explicitly covering manufacturing processes, yields and the cable and connectivity products needed end to end. That is the bridge between a record attenuation number and an operating network, and the cost of installed, tested, maintainable links will matter more than the laboratory figure.
A better stack can make PUE look worse Here is a consequence that never appears in a product announcement: an interconnect improvement can cut a facility’s electricity bill while raising its power usage effectiveness. PUE is total facility energy divided by IT equipment energy. The Green Grid, which invented it, is explicit that it “is not a data center productivity metric” and “does not provide any guidance or insight into the operation or productivity of IT equipment.” It was later standardised as ISO/IEC 30134-2.
Take a facility drawing 100 megawatts for IT and 10 for overhead: PUE 1.10. Now let a networking improvement cut IT demand to 90 while overhead stays at 10. Total draw falls from 110 to 100 megawatts — and PUE rises to 1.11.
The building saves ten megawatts and scores worse on the metric. That is an illustrative example on invented inputs, not a claim that cooling load holds still in a real facility. The same discipline applies to the small numbers.
Five picojoules per bit saved at an aggregate hundred terabits per second is 500 watts — desk arithmetic, and whether it matters depends entirely on how many interfaces run, how hard, and whether the figure covers one end of the link or both. The real question is how much more useful work the complete system does within the same power and reliability envelope. Display factories are an advantage, not a free conversion The industrial crossover is no longer speculative.
On 2 July 2026, Sumitomo Chemical announced that its wholly owned Korean subsidiary Dongwoo Fine-Chem had signed a joint venture agreement — a definitive one — with Samsung Electro-Mechanics: 66 per cent Samsung, 34 per cent Dongwoo, capital of 482.1 billion won, sited at Pyeongtaek, tentatively named GlaSSEM, “scheduled to establish a supply system by the second half of fiscal 2027.” Note that a memorandum between the same parties from November 2025 still circulates in search results with vaguer terms; it is a different, earlier event. At SEMICON Taiwan on 31 August, AUO showed two things: a MicroLED co-packaged-optics module aimed at “high-speed, short-reach interconnects of up to 10 meters,” with transmitters from its group company Ennostar and receivers from Tyntek, and a glass-core substrate pairing Corning’s semiconductor-grade glass with AUO’s redistribution-layer process. Daxin’s dielectric material is described as “expected to be incorporated” — forward-looking, not shipped.
The point is that capability built for consumer glass and displays is becoming relevant to packaging. The asset is not the material. It is handling, patterning and integrating it repeatedly without surrendering the economics to defects.
The geometry can mislead, though. A 510-by-515-millimetre panel has about 3.7 times the gross area of a 300-millimetre wafer — desk arithmetic — and that ratio says nothing about good packages per hour, edge loss, utilisation or cost per qualified part. A large panel is an opportunity to process more material and a larger object that must satisfy the process everywhere it matters.
Panel-scale is an economic hypothesis until somebody ships saleable output. Intel can win packaging without TSMC losing the wafer The competitive story is less zero-sum than the framing suggests, and the best evidence comes from the incumbent. On TSMC’s second-quarter call on 16 July 2026, chairman and chief executive C.C.
Wei was asked about Intel’s EMIB-T — embedded silicon bridges combined with through-silicon vias for vertical power delivery. His answer, on competing packaging capacity: “Our packaging capacity is so tight that now it’s limiting my customers’ growth. We welcome that additional flexibility in the market.
That will help TSMC’s front-end wafer business growth, which is a majority part of TSMC’s business.” And separately, on the distinction itself: “The front end’s wafer business and the back end’s business are two different things, right? If they are the same, you can expect ASE become the front-end competitor also.” That is an unusually useful antidote to winner-take-all thinking. A packaging supplier can take strategically valuable work without capturing the logic fabrication underneath it.
On the same call, Wei said COUPE production had started and would ramp. That is progress on a photonics platform. It is not evidence of high-volume permanent glass-core packaging, and the two should not be filed together.
The questions for a reader holding any of these names are therefore specific. Which manufacturing step changed supplier? Which component entered a finished product?
What revenue and margin attach to it? A packaging qualification, a wafer win and an optical-component order are three different economic events, and collapsing them into one “AI glass” trade destroys the analysis exactly where it needs to get finer. Through March 2028, the base case is coexistence Electrical links, laser optics, developing MicroLED systems, conventional fibre and selected hollow-core routes can all advance at different speeds.
Nothing in the record sets a date when the industry changes materials everywhere. Maturity levels differ more than enthusiasm does. A signed joint venture, an exploratory one-year memorandum, an evaluation kit, a service manual and a production deployment are not equivalent milestones, and the piece above has one of each.
What would move each of them forward is concrete. For glass-core packaging: a named commercial device, a customer qualification, repeat orders, disclosed manufacturing economics. For MicroLED links: full-link measurement rather than 25 channels at a time, connector qualification, field reliability.
For co-packaged optics: evidence that system savings beat integration and service cost. For hollow-core: repeatable installed-link performance and competitive lifecycle cost across more routes. The risks are equally concrete.
Glass-core defects can erase the material advantage. Optical integration can complicate service. MicroLED has to hold its reach and error rate.
And the incumbent approaches keep improving while customers decide. The significance of the glass stack is not that silicon, copper, polymer, or lasers are about to disappear. It is that engineers now have more ways to redistribute the work among them.
A glass core may keep a larger package usable. An array of slow light sources may avoid expensive fast electronics. A connector may make a promising link serviceable.
An air-filled fibre may cut waiting time. Which makes the least glamorous parts the most interesting ones. A better-coated hole.
A cable borrowed from medical imaging. A laser you can replace without disturbing the expensive part of the assembly. The next infrastructure breakthrough in AI may look less like a new brain and more like a system that wastes less of what its brains can already do.
Sources and data notes Every claim above is sorted by what kind of evidence stands behind it. Signed or announced. Intel and Lens Technology, 24 July 2026, a one-year exploratory memorandum on glass-substrate packaging combining Lens’s “precision glass processing, high-precision lasers, and large-scale production capacity” with Intel’s packaging; no volume customer named, and process verification, qualification and mass production each require separate contracts.
Intel’s newsroom page is closed to automated retrieval, so that language reaches this desk through Dow Jones, MarketScreener and eeNews Europe rather than from Intel directly; Digitimes’ 25 July and eeNews’ 27 July are republication dates. Sumitomo Chemical, 2 July 2026, on the Dongwoo Fine-Chem and Samsung Electro-Mechanics joint venture. AUO, 31 August 2026, GlobeNewswire, on both SEMICON Taiwan exhibits.
Corning, 23 September 2025, on manufacturing Microsoft’s hollow-core fiber in North Carolina; a separate 2026 scale-up announcement involving Heraeus is a different event. MediaTek, 17 March 2026. Measured and peer-reviewed.
MOSAIC, ACM SIGCOMM 2025, Coimbra, 8–11 September, best paper: the 100-channel prototype, the 25-channel measurement, 2 Gbps at 20 meters, 1.6 at 30, the 50-meter simulation, the 20-by-20 design calculation and the forwarded-clock proposal. Hollow-core attenuation of 0.091 dB/km at 1,550 nm, Nature Photonics, 1 September 2025, Southampton’s Optoelectronics Research Center with Microsoft Azure Fiber. Intel’s ECTC 2026 material, published 2 June 2026, on glass cores, embedded bridges, copper-filled through-glass vias and co-packaged optics.
Intel’s original glass disclosure, 18 September 2023, for the quoted language and the “second half of this decade” timing. The SeWaRe work: ECTC 2025, Wei and Frederick, revisiting a failure named by Koizumi; mechanism and mitigation as described by the IEEE Electronics Packaging Society’s published tutorial material, with the authors’ affiliation resting on SemiEngineering’s account rather than the paper itself. Vendor estimates.
Microsoft’s late-2027 commercialization target and the roughly 50 percent power comparison against mainstream laser-based cables, from its newsroom feature of 17 March 2026, on its own lab tests; the paper’s own figure is 3.1 to 5.3 watts and 56 to 68 percent, a different claim about a different thing. Microsoft’s 47 percent propagation figure from the Azure blog; coverage of the Nature paper carries 45. Avicena’s August 2026 evaluation kits and its 17 September connectorised demonstration, from the company and trade press; ECOC’s exhibition runs 21–23 September in Málaga, the conference 20–24.
TRUMPF’s HiPIMS claim, 1 September 2026, vendor material relayed through trade press, with no aspect ratio and no yield published. AGC’s 0.8 W/mK and its tunable-CTE range of 3.3 to 12.0 ppm/°C, both from AGC’s own pages, one of them marketing rather than a datasheet, neither independently corroborated. NVIDIA’s external-laser architecture and the XDR replacement procedure come from its developer blog and its switch documentation — operational manuals rather than marketing — which makes them stronger than most vendor material here.
On the record. TSMC’s second-quarter call, 16 July 2026; both C.C. Wei quotations are from that call and from two separate answers, not one passage, and are taken from a commercial transcript rather than TSMC’s own edited version.
This desk’s arithmetic, all on invented inputs. 80 mm × 10 ppm/°C × 200 °C = 160 µm. (1 − 10⁻⁶)^1,000,000 = 36.79 per cent. 110 ÷ 100 = 1.10 and 100 ÷ 90 = 1.111. 5 pJ/bit × 100 Tbit/s = 500 W. (510 × 515) ÷ (π × 150²) = 3.72. 1 − 1/1.47 = 32.0 per cent. Propagation at n = 1.468 is 4.90 µs/km against 3.34 in air, or 490 against 334 µs over 100 km. None of these estimates any named supplier’s yield, power, or return.
Definitions. PUE per The Green Grid’s white paper 49, which originated the metric; later standardized as ISO/IEC 30134-2. ASHRAE harmonized around it and did not define it.
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