TRENDYVEST.COM | DEEP ANALYSIS — PART THREE OF FOUR
By Nicholas Thomas | June 26, 2026

The first two articles in this series covered Amazon and Google — the two hyperscalers with the deepest custom silicon programs, the longest track records, and the most consequential customer commitments. But the AI chip war is not a two-player game. It never was.

Meta has been building its own inference chips since 2020 and just announced four new generations on a six-month release cadence. Microsoft deployed its Maia 200 accelerator in January 2026 and is running OpenAI's GPT-5.2 models on it today. AMD has secured a $90 billion strategic partnership with OpenAI and is shipping the MI400 series on TSMC's 2nm process. Cerebras built a chip the size of an entire silicon wafer and is generating 969 tokens per second on models that take GPU clusters hours to run. OpenAI is building its own chip. xAI just placed a major ASIC order with Broadcom. And Nvidia — which we haven't forgotten — bought the most dangerous inference startup in the market for $20 billion and is now facing a Senate antitrust inquiry over it.

This is the rest of the field. And it is larger, more technically sophisticated, and more commercially serious than almost any mainstream coverage has conveyed.META

MTIA: SIX CHIP GENERATIONS IN TWO YEARS, AND THE PACE IS ACCELERATING

Start with the company that most people think of as a social media business but is quietly running one of the most aggressive custom silicon programs in the industry.

Meta's MTIA — the Meta Training and Inference Accelerator — began as an internal project in 2020 focused on a very specific problem: ranking and recommendation inference. Every time Facebook loads your feed, Instagram ranks posts, or WhatsApp sorts messages, that process runs on deep learning recommendation models that require enormous memory bandwidth and high throughput at relatively low batch sizes. Standard Nvidia GPUs were designed for large-batch training workloads. They were expensive, power-hungry, and inefficient for the specific demands of Meta's inference stack. So Meta built a chip designed around the actual bottleneck.

The first two generations — retroactively renamed MTIA 100 and MTIA 200 — were detailed in papers at ISCA 2023 and ISCA 2025. MTIA 100 was modest: 64 processing elements in an 8x8 grid, LPDDR5 memory rather than HBM, etched in TSMC's 7nm process, running at 800 MHz on a form factor small enough to mount on an M.2 board. Purpose-built, not powerful. MTIA 200 doubled the compute and memory bandwidth, demonstrated 3.5 times the dense compute performance of MTIA 100, and began proving that the architecture was scalable.

Then on March 11, 2026, Meta announced four entirely new generations simultaneously — MTIA 300, 400, 450, and 500 — all co-developed with Broadcom, all fabricated by TSMC, all built on RISC-V architecture, and all designed to share the same chassis, rack, and network infrastructure so that each successive generation can drop into the existing physical footprint without requiring new data center buildouts.

According to Tom's Hardware and Meta's own technical blog, from the MTIA 300 through to the MTIA 500, HBM bandwidth increases 4.5 times and compute FLOPs increase 25 times across the lineup. The MTIA 300 is already in production, powering the ranking and recommendation models behind Facebook, Instagram, and WhatsApp's feeds. The MTIA 400 — described by Meta as its first chip with "raw performance competitive with leading commercial products," a carefully chosen phrase that means competitive with Nvidia — is completing testing ahead of data center deployment. The MTIA 450, which doubles HBM bandwidth over the 400 and targets generative AI inference, arrives in the second half of 2026. The MTIA 500 follows in 2027, adding another 50% HBM bandwidth on top of the 450.

The six-month release cadence is the story. Nvidia ships new GPU generations every 18 to 24 months. AMD targets roughly annual cycles. Meta is shipping production silicon every six months. As Meta's VP of Engineering Yee Jiun Song explained, this pace is "necessary to keep up with the speed at which we're expanding our data center footprint" — and that footprint is enormous. Meta's 2026 capital expenditure guidance sits at $115 to $135 billion, with the Hyperion data center campus in Louisiana targeting 5 gigawatts of compute capacity, enough to power roughly 3.7 million average American homes.

Meta achieves this velocity through what it calls modular chiplet architecture — reusable components across all levels of the design from processing elements to chassis to rack to network. The MTIA 400, 450, and 500 all share the same physical infrastructure, meaning Meta's data center construction teams can build the facility once and upgrade the compute through successive chip generations without rebuilding the physical environment. That is an extraordinarily capital-efficient approach to chip development at scale.

The TCO story is compelling. According to Medium's technical deep dive on MTIA, the program has already achieved a 44% reduction in total cost of ownership versus GPUs for ranking and recommendation inference workloads — the same metric class that Google achieved with TPUs. Hundreds of thousands of MTIA chips are in production today. The program has onboarded numerous internal Meta production models and tested against large language models including Llama.

What MTIA is not, and what Meta is explicit about, is a full Nvidia replacement. Meta maintains what it calls a "portfolio approach" — MTIA handles recommendation training and generative AI inference, while Nvidia H100, H200, and B200 GPUs continue to handle frontier model training and peak capacity workloads. The strategic logic is diversification rather than displacement: every dollar of inference cost shifted to MTIA is a dollar no longer paid to Nvidia at Nvidia's margins, while Nvidia's training dominance is acknowledged rather than challenged directly. This is the most commercially honest framing of any hyperscaler's custom silicon strategy — and it is also the most replicable.

MICROSOFT MAIA 200: THE INFERENCE CHIP THAT RUNS OPENAI'S MODELS TODAY

Microsoft's custom silicon story is shorter than Google's or Amazon's, but the January 2026 Maia 200 announcement — and more importantly, its immediate production deployment — established Microsoft as a serious participant in the hyperscaler chip race rather than an observer.

According to Microsoft's official blog, confirmed by Tom's Hardware and GeekWire, Maia 200 is built on TSMC's 3nm process with more than 140 billion transistors and is purpose-built for AI inference. The specifications are significant: more than 10 petaflops of FP4 compute, more than 5 petaflops of FP8, 216 GB of HBM3e at 7 terabytes per second of bandwidth, and 272 MB of on-chip SRAM within a 750-watt thermal envelope. That SRAM allocation — 272 MB — is notably larger than Nvidia's deployed Blackwell B200, which carries 192 MB. More on-chip SRAM means more data stays close to the compute engines rather than being fetched from slower HBM, which directly translates to lower latency in inference workloads where small details like that compound across billions of daily requests.

Microsoft claims Maia 200 delivers three times the FP4 performance of Amazon's Trainium3 and exceeds Google's Ironwood TPU v7 on FP8 performance. Those claims come from Microsoft's own benchmarks and should be treated with appropriate skepticism — internal benchmarks for inference-optimized chips are highly workload-dependent, and the comparison methodology is not independently verified. What is not in dispute: Maia 200 is deployed today, running OpenAI's GPT-5.2 models in production at Microsoft's US Central datacenter in Des Moines, Iowa, with the US West 3 Phoenix datacenter coming next. Microsoft says AI models were running on Maia 200 silicon within days of receiving the first packaged chips, and the time from first silicon to datacenter deployment was compressed to an unusually short window.

Beyond GPT-5.2 inference, Microsoft's Superintelligence team is using Maia 200 for synthetic data generation and reinforcement learning — the critical feedback loops that train next-generation models. That use case is strategically significant. Synthetic data generation is one of the most compute-intensive processes in modern AI development, and running it on proprietary silicon at 30% better cost efficiency than the existing GPU fleet directly accelerates Microsoft's ability to improve its internal models.

The software strategy is worth noting. Microsoft built Maia's SDK on Triton — an open-source compiler with significant contributions from OpenAI. This is a deliberate attempt to reduce the friction of the CUDA-to-Maia migration path by using a tool that OpenAI's engineers already know and that is becoming increasingly standard across the AI development community. The Maia SDK is currently in preview for select partners rather than generally available, which reflects both the chip's production maturity and Microsoft's cautious approach to external deployment.

Techzine's interview with Microsoft's Azure Maia chief captured the strategic positioning precisely. Maia 200 sits, in his framing, "somewhere in the middle of a generalized parallel processor like a GPU and a specialized chip such as Cerebras' CS-3 and Groq's LPU." It is not a training chip — Microsoft explicitly does not position it as competing with Nvidia for frontier model training. It is not maximally specialized — it preserves enough general-purpose capability to handle future AI workload architectures that cannot be fully predicted today. It is an inference chip designed for the known demands of 2026 with enough flexibility to remain relevant into 2027 and 2028, which is the right design philosophy for a company that cannot afford to bet on a single architectural direction when its largest customer, OpenAI, is evolving its model architecture continuously.

AMD MI400 SERIES: THE ONLY MERCHANT CHIP THAT GENUINELY THREATENS NVIDIA

Of all the companies in this series, AMD is the only one attempting to challenge Nvidia in the open merchant market — not as a captive internal chip for a hyperscaler's own workloads, but as a product that any customer can purchase, deploy, and use in any data center environment they choose.

AMD unveiled the full MI400 series at CES 2026 on January 5, with CEO Lisa Su presenting five distinct accelerators targeting different segments of the AI and high-performance computing market. All share the CDNA 5 architecture and are built on TSMC's 2nm process — making them the first production AI GPUs to use the most advanced node available anywhere in the semiconductor industry.

The flagship MI455X is the one that matters most for the AI training market. According to AMD's official specifications, confirmed by TweakTown, Data Center Dynamics, and ServeTheHome, it packs 320 billion transistors across 12 TSMC 2nm compute chiplets and 3 advanced 3nm chiplets, delivering up to 40 petaflops of FP4 performance and 20 petaflops at FP8 precision. Memory is 432 GB of HBM4 — a 50% increase over the MI350's 288 GB of HBM3e — at 19.6 terabytes per second of bandwidth, more than double the MI350's 8 terabytes per second. Scale-out bandwidth sits at 300 GB per second per GPU.

At rack scale, the Helios system — AMD's first integrated rack-scale AI architecture announced at CES 2026 — packs 72 MI455X accelerators with 31 terabytes of HBM4 and 1.4 petabytes per second of aggregate memory bandwidth, delivering 2.9 FP4 exaflops for AI inference and 1.4 FP8 exaflops for training. For the MI450X IF128 variant targeting late 2026, 128 GPUs linked at rack scale deliver a combined 6,400 petaflops and 36.9 terabytes of high-bandwidth memory — a system AMD claims surpasses Nvidia's Vera Rubin VR200 NVL144 in both raw memory capacity and scale-out bandwidth at rack level.

The OpenAI deal is the anchor that validates the MI400's commercial traction. In October 2025, AMD announced a strategic partnership with OpenAI for the supply of 6 gigawatts of MI450 GPUs — a commitment worth approximately $90 billion according to IntuitionLabs' analysis. OpenAI said it would build a 1 gigawatt data center using AMD MI450 chips starting in 2026. OpenAI co-founder Greg Brockman joined Lisa Su on stage at the announcement. For a company that has historically been dominated by Nvidia for virtually all serious AI training, having OpenAI as a committed customer represents the most significant commercial validation in AMD's data center history.

AMD also earned what the company described as equity-linked warrants allowing OpenAI to own up to 10% of AMD shares as part of the partnership structure — a detail that transforms the relationship from a vendor agreement into a strategic alignment with significant financial implications for both parties.

The ROCm software ecosystem — AMD's CUDA equivalent — remains the most frequently cited concern by developers evaluating a switch from Nvidia. The gap has narrowed meaningfully through 2025 and 2026, with ROCm now supporting PyTorch natively and achieving compatibility with most major training frameworks. But the optimization depth, the library breadth, and the developer community around CUDA still represent a meaningful migration cost. AMD's strategy is to make ROCm good enough that the price-performance advantage of the MI400 series justifies the switching friction — and for hyperscale customers with dedicated software engineering teams who can absorb that investment, it increasingly does.

MI500, targeting 2027 on CDNA 6 with TSMC 2nm enhanced process and HBM4e, is already on AMD's public roadmap. The MI500 UAL256 mega pod will scale to 256 GPUs — another generation of rack-scale escalation that signals AMD's commitment to playing at the same system-level scale as Nvidia's most ambitious architectures.

THE STARTUPS: NICHE DOMINANCE, SPECTACULAR EXITS, AND ONE EXTRAORDINARY MACHINE

The startup layer of the AI chip market deserves more analytical attention than it typically receives — not because any of these companies will displace Nvidia in the near term, but because they are defining the technological frontier of what AI hardware can be when unconstrained by the need for backward compatibility with CUDA or the design tradeoffs that come with general-purpose architecture.

Cerebras: The Chip That Shouldn't Exist

Cerebras Systems built something the semiconductor industry said was impossible. The Wafer-Scale Engine 3 — WSE-3 — is not a chip in the conventional sense. It is an entire 300mm silicon wafer etched with 4 trillion transistors, 900,000 AI cores, and 44 gigabytes of on-chip SRAM across a 46,225 square millimeter die. For context, Nvidia's largest GPU is roughly 800 square millimeters. The WSE-3 is 57 times larger.

The performance consequences of that size are profound. According to Big Data Supply's analysis, Cerebras' CS-3 system generates 969 tokens per second on Llama 3.1-405B — 75 times faster than comparable GPU hyperscaler solutions. The system outperforms Nvidia's DGX B200 Blackwell GPU by 21 times on inference throughput while using one-third the cost and power. The reason is architectural: when a model fits entirely on-chip — which is possible with the WSE-3's 44 GB of SRAM — you eliminate the memory bandwidth bottleneck that constrains every GPU-based inference system. There are no memory fetches, no HBM latency, no multi-chip communication overhead. The computation is entirely local.

Cerebras raised $1 billion at a $23 billion valuation and has contracted $10 billion in infrastructure with OpenAI for 750 megawatts of compute through 2028. The company has been refiling for a public offering. Its path to broad market adoption is constrained by the wafer-scale approach's fundamental limitation: models must fit within the WSE-3's memory footprint, which excludes the very largest frontier models. But for the specific workload of fast inference on large-but-not-largest models, nothing in the market comes close.

Groq: The Fastest Inference Engine Ever Built — Now Inside Nvidia

Groq was founded by Jonathan Ross, one of the original engineers behind Google's TPU. The company built the Language Processing Unit — an inference accelerator using deterministic static scheduling rather than the dynamic execution that GPUs use. By eliminating the hardware complexity required for dynamic scheduling, Groq achieved inference speeds of 276 to 300 tokens per second on Llama 70B at standard performance, scaling to 1,665 tokens per second with speculative decoding. The company had 2 million developers on GroqCloud and raised $750 million in September 2025 at a $6.9 billion valuation.

Then Nvidia bought it. In what CNBC confirmed as Nvidia's largest acquisition on record, the company paid approximately $20 billion for Groq's assets — 2.9 times the startup's most recent valuation. The structure was unusual enough to attract regulatory attention: rather than a conventional acquisition that would trigger Hart-Scott-Rodino premerger review, Nvidia licensed Groq's technology and hired its leadership while nominally leaving the company independent. In March 2026, Senators Elizabeth Warren and Richard Blumenthal sent a formal letter to Nvidia questioning whether the deal constitutes an illegal attempt to evade antitrust laws. As of publication, no FTC or DOJ enforcement action has been announced, but the inquiry signals that legislators are actively working to close what they characterize as a "merger in disguise" loophole.

The acquisition reveals something important about how seriously Nvidia takes inference competition. A company that controls 92% of the AI GPU market does not pay $20 billion for a startup unless it considers that startup a genuine threat. Groq was winning inference speed benchmarks in ways that embarrassed Nvidia hardware, had a growing developer community, and was converting its speed advantage into commercial traction. Nvidia's response was to absorb it — a move that simultaneously eliminated a competitor and brought deterministic scheduling architecture inside Nvidia's own research pipeline.

Tenstorrent: Jim Keller's Open Silicon Bet

Tenstorrent is led by Jim Keller — the architect behind AMD's Zen CPU that rescued the company in 2017, Apple's A-series processor family, Tesla's Full Self-Driving chip, and multiple other defining silicon programs across the industry. His presence at Tenstorrent signals a serious technology bet, and his track record suggests the bet is worth watching.

Tenstorrent's approach is built on RISC-V open architecture and a flexible business model that spans IP licensing, chiplet sales, and complete systems. The Blackhole chip — 140 Tensix++ cores, 6nm process, 774 teraflops of FP8 performance — is the current generation product. The company raised $693 million in a Series D led by Samsung Securities, demonstrating confidence in the RISC-V approach among sophisticated semiconductor investors. Tenstorrent's strategic differentiation is openness: where every hyperscaler custom chip is locked to its own ecosystem, Tenstorrent is building a platform that any developer, any company, and any government can deploy independently of cloud vendor relationships.

OpenAI Titan: The AI Lab That's Building Its Own Silicon

The most surprising entrant in the custom chip market is not a semiconductor company or a hyperscaler. It is OpenAI.

According to IntuitionLabs' analysis confirmed by multiple semiconductor sources, OpenAI and Broadcom formally announced a strategic collaboration in October 2025 to co-design and deploy 10 gigawatts of OpenAI-designed AI accelerators. The custom chip — codenamed Titan — is built on TSMC's 3nm process using a systolic array architecture optimized for AI inference with HBM3e and HBM4 memory. Deployment is targeted for the second half of 2026, with a second generation planned on TSMC's A16 process. OpenAI has simultaneously committed to 10 gigawatts with Nvidia, 6 gigawatts with AMD, and 2 gigawatts with Amazon Trainium — a multi-vendor compute strategy that turns the entire AI chip market into a competitive auction for OpenAI's infrastructure dollars.

The significance of OpenAI building its own chip cannot be overstated. OpenAI is not a hardware company. It is not a cloud provider. It is an AI research and product company that became so large, and so expensive to operate, that it concluded building its own silicon was economically necessary. That conclusion — reached by the most prominent AI company in the world — is the clearest possible signal that Nvidia's pricing power has reached the level where even OpenAI cannot sustain it without alternative supply.

xAI: The Newest Entry

Elon Musk's xAI recently placed a major ASIC order with Broadcom for a custom inference chip targeting mass production in 2027. Details are limited, but the strategic logic is identical to every other player in this field: xAI is scaling Grok's serving infrastructure rapidly, the marginal cost of Nvidia inference hardware is a meaningful constraint on how aggressively it can price its AI products, and the payback period on custom silicon at xAI's projected scale is compelling.

BROADCOM: THE HIDDEN ARCHITECT OF EVERYTHING

No discussion of the custom AI chip market is complete without confronting the one company whose name appears in the background of virtually every program covered in this series.

Broadcom designs Google's TPU — confirmed through at least 2031 by a Broadcom SEC filing. Broadcom co-develops Meta's MTIA. Broadcom is co-designing OpenAI's Titan. Broadcom is believed to be working with xAI. According to Counterpoint Research, Broadcom is projected to capture 60% of the custom AI chip market by 2027.

This creates a paradox. The coordinated effort to challenge Nvidia's dominance — which we will examine fully in the fourth and final article in this series — is substantially powered by a single company that is also Nvidia's strategic partner on networking silicon. Broadcom is simultaneously the architect of the coalition against Nvidia and a major vendor to Nvidia itself. It is the one company in the AI hardware market that profits regardless of which side wins.

THE MARKET CONTEXT: HOW FAR THE FIELD HAS ACTUALLY COME

Step back from the individual programs and a structural picture emerges that is more consequential than any single announcement.

According to TrendForce, 27.8% of AI servers shipped in 2026 will be ASIC-based, up from roughly 15% in 2023. Custom ASIC shipments are growing at 44.6% year over year, compared to 16.1% for merchant GPUs. XPU accelerators are expected to lead growth at 22% in 2026, outpacing GPUs at 19% and CPUs at 14%.

The AI inference market is projected to reach $255 billion by 2030, growing at a 17 to 19% compound annual rate. By 2030, inference will represent 75% of all AI compute demand. That is the market that every custom silicon program in this series is positioned to address — and it is a market that Nvidia, despite its extraordinary position in training, does not own by default.

Nvidia's FY2026 revenue reached $215.9 billion — up 65% year over year — with data center revenue at $193.7 billion. The company commands approximately 92% of the discrete GPU market. Those numbers are extraordinary. They are also the highest-profile target in technology investing, and they are the reason every company covered in this series is spending billions to build an alternative.

None of them will replace Nvidia. That is not the point. The point is that by 2028, the AI hardware market will be genuinely multi-vendor for the first time since Nvidia established its monopoly in 2022. The inference layer — where most of the economics ultimately live — will be contested territory. And the companies that control their own silicon for the workloads they run most frequently will have a structural cost advantage over those that don't.

THE BOTTOM LINE

This is a field of twelve serious competitors, each attacking Nvidia from a different direction with a different architecture, a different business model, and a different theory of what AI hardware needs to be.

Meta is winning on inference cost reduction and development velocity. Microsoft is winning on integration with the world's most commercially important AI model. AMD is the only merchant chip that any developer can actually buy and deploy anywhere. Cerebras is winning on raw inference speed for models that fit on-chip. OpenAI is building its own silicon because the economics demanded it. And Broadcom is quietly designing chips for all of them.

No single company in this article is going to take Nvidia's crown. But together — and the together is the story — they are doing something more consequential than any individual challenge. They are dismantling the conditions that allowed a single company to control the infrastructure of the AI revolution.

The fourth and final article in this series will examine that coalition as a unified phenomenon: who is coordinating, how the strategy is evolving, what it has already achieved, and what it means for the future of Nvidia, for AI economics, and for every investor and builder trying to navigate what comes next.

Next: The Coalition — how Amazon, Google, Meta, Microsoft, AMD, OpenAI, and the startup ecosystem are executing the most coordinated challenge to a single technology company's dominance since the browser wars.

— Nicholas Thomas | TrendyVest.com | June 26, 2026