GOOGLE'S CHIP PROGRAM IS THE OLDEST, THE DEEPEST, AND THE MOST DANGEROUS THREAT TO NVIDIA THAT NOBODY IS FULLY TAKING SERIOUSLY.

TRENDYVEST.COM | DEEP ANALYSIS — PART TWO OF FOUR By Nicholas Thomas | June 26, 2026

In 2013, Jeff Dean — the engineer who helped build Google Search, Gmail, and YouTube's infrastructure — ran a calculation that alarmed him.

He and the Google Brain team were looking at the potential compute load of a simple new feature: Google voice search. If every Android user talked to their phone for just three minutes a day, the analysis showed Google would need to double its entire global data center capacity to handle the processing.

"We thought surely there must be a better way," Dean later told Google's blog.

That search for a better way produced the Tensor Processing Unit — the TPU. A chip built for one specific purpose: doing the matrix multiplication that powers machine learning faster, cheaper, and more efficiently than any general-purpose GPU could. It has been running inside Google's data centers since 2015, powering every Google Search query, every YouTube recommendation, every Gmail spam filter, every Translate request, and every generation of Gemini.

Google has now built eight generations of this chip. And the eighth generation — announced at Google Cloud Next on April 22, 2026 — represents a decision so significant that it deserves to be understood not just as a chip announcement but as a philosophical statement about where AI computing is going and who will control it.

This is the full story of the TPU. Where it came from, what it has become, what makes it categorically different from every other chip in this series, and why the company that built the Transformer architecture, invented JAX, trained Gemini entirely on custom silicon, and is now selling its chips to Anthropic, Meta, and Midjourney may be the most underestimated force in the AI hardware market.

THE ORIGIN: A NAPKIN CALCULATION THAT CHANGED THE INDUSTRY

The TPU did not emerge from a competitive analysis of Nvidia's roadmap. It emerged from an internal crisis about Google's own economics.

As Jeff Dean explained in a Google blog post marking the TPU's tenth anniversary, the voice search calculation in 2013 was the trigger: "We realized we'd need to double the number of computers in Google data centers to support these new features." The team looked at existing hardware on the market. Nothing could meet the demand efficiently. So they built something new.

The original TPU — publicly announced at Google I/O in May 2016, confirmed to have been running inside Google's data centers since 2015 — was a radically focused design. No rasterization. No texture mapping. No gaming pipeline. Just one thing: fast, power-efficient matrix multiplication for neural network inference. According to Google's landmark 2017 paper presented at the International Symposium on Computer Architecture, the first TPU achieved 15 to 30 times higher performance and 30 to 80 times better performance per watt than contemporary CPUs and GPUs for neural network inference workloads.

What followed was a decade of iteration that most of the industry failed to track because Google kept the chips entirely internal. While Nvidia was staging product launches and building developer communities around CUDA, Google was quietly running the largest fleet of custom AI accelerators in the world — powering its own products, training its own models, and building the software infrastructure to make the chips useful at massive scale.

By 2017, Google was processing more than 100 petaflops of neural network inference per day on TPUs — workloads that would have been economically impossible on CPUs. The company that invented the Transformer architecture, which underpins every major AI model in existence today, was doing it on chips nobody else could use.

That era ended in 2018, when Google opened Cloud TPUs to third-party customers. And what began as an internal cost-cutting tool is now the foundation of a commercial chip business that is reshaping the AI infrastructure market.

SEVEN GENERATIONS IN ELEVEN YEARS: WHAT THE EVOLUTION ACTUALLY MEANS

Understanding what makes the TPU's current generation special requires understanding what the program has been building toward across eight generations.

The first TPU was inference-only — it could run trained models but could not train them. TPU v2, launched in 2017, was the first to handle both training and inference, enabling Google to train PaLM — a 540-billion parameter language model — on 6,144 TPU v4 chips using the Pathways distributed training system. That achievement, documented in a Google research paper, was a proof of concept that large-scale distributed AI training on custom silicon was not just possible but economically superior to GPU-based alternatives.

Each subsequent generation delivered meaningful leaps. TPU v5e and v5p improved the performance-per-dollar across different workload types. TPU v6e — codenamed Trillium — delivered 4.7 times the peak compute of v5e and was the first generation to achieve 99% scaling efficiency at MLPerf Training benchmarks, the industry's standard measure of distributed training performance. More than 100,000 Trillium chips are currently deployed globally according to Nerd Level Tech's custom chip analysis.

Then came Ironwood. And the numbers stopped being incremental.

IRONWOOD: THE CHIP THAT CHANGED THE CONVERSATION

Google's seventh-generation TPU — Ironwood, or TPU v7 — was announced at Google Cloud Next 2025 and reached general availability in April 2026. It is the chip that finally forced the AI infrastructure market to take the TPU program seriously as a genuine Nvidia alternative rather than an interesting internal curiosity.

According to Google's official Cloud documentation, confirmed by Tom's Hardware and TechPowerUp, each Ironwood chip delivers 4,614 FP8 teraflops of compute — essentially matched with Nvidia's Blackwell B200 at 4,500 TFLOPS, a near-tie at the individual chip level. Each chip carries 192 GB of HBM3e memory with 7.37 terabytes per second of bandwidth — higher memory capacity per chip than any comparable Nvidia offering at launch.

But where Ironwood becomes genuinely extraordinary is at pod scale. TPU pods scale to 9,216 chips in a single connected system — 128 times more processing units than Nvidia's GB300 NVL72, which maxes out at 72 GPUs. A fully configured Ironwood pod delivers 42.5 FP8 exaflops of compute, carries 1.77 petabytes of HBM3e memory in total, and is interconnected using a proprietary 9.6 terabits-per-second Inter-Chip Interconnect network that Google has been refining since TPU v2 in 2017.

For context on what 42.5 exaflops means: according to Google's official Ironwood blog post, this exceeds the compute power of the world's largest supercomputer by more than 24 times. A single TPU pod can do more computation than the most powerful dedicated scientific computing system ever built. And Google is deploying hundreds of these pods.

The TCO story is as important as the performance story. According to SemiAnalysis's independent analysis, the all-in total cost of ownership for a full Ironwood 3D Torus configuration is approximately 44% lower than the equivalent cost of a GB200 server from Nvidia. Independent benchmarks published by SemiAnalysis in February 2026 put Ironwood's cost at $0.18 per million tokens for Gemini inference, versus $0.31 per million tokens on comparable B200 configurations — a 42% TCO advantage that compounds at hyperscaler volume. Midjourney migrated from Nvidia GPUs to Google TPUs and reduced its monthly inference spend from $2.1 million to under $700,000 — a $16.8 million annualized saving — while maintaining output quality.

The interconnect is the detail that the spec sheets don't fully capture. Google has been building its Inter-Chip Interconnect — ICI — as a proprietary scale-up network since TPU v2. Where Nvidia's NVLink maxes out at 576 GPUs in a single NVLink domain, ICI connects 9,216 chips in a single Ironwood pod. The networking advantage at scale is the TPU's most durable competitive differentiator — and it is one that Nvidia, despite its extraordinary resources, has not been able to replicate.

THE CUSTOMERS: WHEN ANTHROPIC AND META CHOOSE YOUR CHIP, THE ARGUMENT IS OVER

The most compelling proof of Ironwood's viability is not a benchmark. It is the customer list.

Anthropic — the company that builds Claude, one of the two or three most commercially important AI models in the world — signed what Google described as the largest TPU deal in its history. According to CNBC and Google's official announcements, Anthropic committed to deploying up to one million Ironwood chips with more than a gigawatt of capacity in 2026. The first phase covers 400,000 units worth an estimated $10 billion in finished racks from Broadcom. The remaining 600,000 are rented through Google Cloud Platform.

That commitment has since expanded. According to The Next Web's reporting confirmed by a Broadcom SEC filing, Anthropic's deal now covers 3.5 gigawatts of TPU compute coming online in 2027 — positioning it as the anchor customer for eighth-generation TPUs as well. Anthropic's run-rate revenue surpassed $30 billion in April 2026, up from roughly $9 billion at the end of 2025, and the company described itself as "compelled by the impressive price-performance gains" from the TPU architecture. Crucially, Anthropic did not abandon Nvidia or Amazon Trainium to do this. It maintains deployments on all three platforms simultaneously — the clearest possible signal that the AI infrastructure market has fractured from Nvidia-only into a multi-platform reality.

Meta has also signed on as a TPU customer, confirmed by SemiAnalysis reporting in November 2025. Safe Superintelligence — Ilya Sutskever's new company — is among the external customers being targeted. Salesforce and Midjourney are confirmed existing customers. According to Google Cloud's own anniversary blog post, more than 60% of funded generative AI startups and nearly 90% of generative AI unicorns now use Google Cloud's AI infrastructure including Cloud TPUs.

The scale of that penetration is remarkable for a chip architecture that was entirely internal as recently as 2018.

THE INTERNAL SQUEEZE: GOOGLE IS RUNNING OUT OF ITS OWN CHIPS

Here is the detail from the Ironwood story that reveals just how much demand the chip has generated — and it is not a comfortable detail for Google.

Bloomberg reported in May 2026 that Google's own DeepMind researchers are now queuing for access to the same TPUs the company is selling in record volume to Anthropic and Meta. The internal compute squeeze is affecting flagship research timelines and has become a factor in researcher departures. According to Metaintro's labor market analysis, senior researchers including long-tenured DeepMind contributors are leaving for compute-rich startups where access to silicon is guaranteed rather than managed as an internal allocation.

The Anthropic deal alone covers 5 gigawatts of TPU capacity and is worth up to $40 billion, according to Metaintro's reporting — turning chips that once served Google's internal research teams into revenue locked up for paying customers. Google is currently bringing more than one gigawatt of new AI compute capacity online in 2026 on top of the gigawatt already serving Anthropic. Even at that pace, the demand is outrunning the supply.

This dynamic reveals something important about the TPU's commercial viability that no benchmark can capture. When a company's own most sophisticated internal users are being outbid for access to its hardware by external customers willing to pay $40 billion for it, the economic case is settled. The TPU is not a charity project. It is a product that the market wants at a price that works.

THE EIGHTH GENERATION: THE MOST CONSEQUENTIAL DECISION IN TPU HISTORY

At Google Cloud Next on April 22, 2026, Google made the most significant architectural announcement in the TPU program's decade of existence. For the first time since Jeff Dean's team built the original chip, Google is splitting the TPU into two separate products designed from the ground up for different workloads.

TPU 8t — codename Sunfish, designed by Broadcom — is purpose-built for large-scale model training. According to Google's official technical deep dive, confirmed by The Register, Tom's Hardware, and Data Center Dynamics, it delivers 12.6 FP4 petaflops of compute per chip with 216 GB of HBM3e at 6.5 terabytes per second of bandwidth. At superpod scale — 9,600 chips — it delivers 121 FP4 exaflops of compute with two petabytes of shared HBM. That is nearly triple the compute of an Ironwood pod at the same scale. Google claims 2.7 to 2.8 times better training price-performance over Ironwood.

The networking architecture is the most striking advancement. The new Virgo Network fabric can link more than 134,000 TPU 8t chips in a single data center with 47 petabits per second of bisection bandwidth — a non-blocking fabric that eliminates the network congestion that kills efficiency in large distributed training runs. Combined with JAX and Google's Pathways software, TPU 8t enables training clusters that scale beyond one million chips across multiple geographic sites operating as a single logical training job. That scale has never existed in the GPU ecosystem. Nvidia's NVLink maxes out at 576 GPUs per domain.

TPU 8i — codename Zebrafish, designed by MediaTek — is purpose-built for inference. The design philosophy is inverted from the training chip. Where TPU 8t optimizes for raw compute throughput, TPU 8i optimizes for memory and latency. Each chip carries 288 GB of HBM — 33% more than the training chip — with 8.6 terabytes per second of bandwidth, 384 MB of on-chip SRAM triple that of Ironwood, and a new Collectives Acceleration Engine that cuts synchronization latency by five times for the all-reduce and all-gather operations that create bottlenecks in large Mixture-of-Experts inference workloads.

Google claims 80% better inference performance per dollar versus Ironwood. At pod scale of 1,152 chips, TPU 8i delivers 11.6 FP8 exaflops. Both chips target TSMC's 2nm process node — the most advanced manufacturing generation — with general availability targeted for late 2027.

The decision to split the line is not just a product decision. It is a philosophical statement. As Google SVP and Chief Technologist Amin Vahdat said at the announcement: "By customizing and co-designing silicon with hardware, networking, and software, we can deliver dramatically more power efficiency and absolute performance." The company is acknowledging what the AI infrastructure market has been learning through painful experience: training and inference are not the same problem, and trying to solve both with the same hardware is an economic compromise that neither workload requires.

THE BROADCOM ANGLE: THE OVERLOOKED WINNER IN EVERY TPU GENERATION

A detail that appears in almost no consumer coverage of the TPU story but matters enormously for investors: Broadcom designs Google's TPU chips. Not manufactures — designs. TSMC manufactures them. But the silicon architecture, from Ironwood through TPU 8t and beyond, is a Broadcom product.

According to a Broadcom SEC filing cited by The Next Web, Broadcom's relationship with Google extends through at least 2031. Mizuho analysts estimate Broadcom's AI custom-silicon revenue from Google alone is projected to approach $42 billion in 2027. For TPU 8i, Google added MediaTek as a second design partner — ending Broadcom's exclusive arrangement and creating competition that Bank of America analyst Vivek Arya estimates could reduce per-chip cost by up to 30%.

The multi-supplier architecture extends further. Google has added Marvell as a networking ASIC partner and Intel Foundry Services as a secondary fabrication option for next-generation chips starting in 2028 — a dual-fab model that mirrors how Apple diversified its iPhone chip manufacturing to gain pricing leverage over TSMC. Every layer of the TPU supply chain is being deliberately diversified to eliminate the single-supplier dependencies that gave Nvidia pricing power over everyone who had no alternative.

Google is projected to ship 4.3 million TPU units in 2026, rising to 10 million in 2027 and more than 35 million in 2028, according to The Next Web's reporting. Those numbers, if realized, would make the TPU program the largest custom silicon deployment in the history of computing.

THE JAX QUESTION: GOOGLE'S HIDDEN SOFTWARE ADVANTAGE

There is a dimension of the TPU competitive story that is almost entirely absent from market analysis but may be the most strategically significant of all. The software.

While Nvidia built its competitive moat on CUDA, Google built something different. JAX — a Python library for high-performance numerical computation that Google developed internally and open-sourced in 2018 — is the programming framework that makes TPUs genuinely productive. Where CUDA is a hardware abstraction layer that lets developers write code that runs on Nvidia silicon, JAX is a mathematical computing system that enables automatic differentiation, hardware-accelerated numerical computation, and distributed training across thousands of chips with elegantly simple Python code.

The research community that uses JAX is not the same as the developer community that uses CUDA. It skews toward academic researchers, theoretical AI scientists, and the engineers at frontier labs who care most about expressibility and mathematical precision. Anthropic uses JAX. Google DeepMind uses JAX. The Transformer paper that started the modern AI era was built at a Google Brain team that was developing what would become JAX and TPUs simultaneously.

According to Uncoveralpha's analysis, a former Google Cloud employee who worked on the TPU program argued that the rate of TPU performance improvement per dollar, generation to generation, has been faster than Nvidia's equivalent improvement. Google stated at Hot Chips 2025 that TPU v7 Ironwood delivers 100% better performance per watt than TPU v6e Trillium. The trajectory of improvement across the TPU program has not slowed. If anything, with the bifurcation into purpose-built training and inference silicon, it is accelerating.

The challenge Google faces is the same one Amazon faces with Trainium: CUDA's penetration is so deep that most developers will not invest in learning a new programming model unless the economics are overwhelming. For inference workloads — which by 2030 will represent 75% of all AI compute demand according to Introl's analysis — the CUDA dependency is weaker than in training. Engineers care about latency and cost per token, not which framework they wrote the serving code in. That is the market opening the TPU 8i is designed to exploit.

WHAT THIS MEANS FOR NVIDIA

Nvidia is not losing the AI chip market to Google's TPU. That is the wrong frame. What is happening is more precise and more consequential.

Google is winning the workload that matters most at the frontier — the training of the largest models that define the competitive landscape of AI. Every generation of Gemini has been trained entirely on TPUs. Anthropic is now training Claude on TPUs and Trainium. The companies building the most advanced AI systems in the world are not using Nvidia for their most critical training workloads. They are using custom silicon.

At the same time, Nvidia still manufactures the hardware that the vast majority of AI companies — the thousands of startups, the enterprise customers, the research labs — use for everything from experimentation to production inference. CUDA's grip on the developer ecosystem is real. The flexibility of a GPU that runs anywhere is real. And as The Register's reporting notes, Google itself announced plans to deploy Vera Rubin NVL72 instances running over the Virgo Network fabric at Cloud Next — meaning Google is simultaneously its own most sophisticated TPU user and one of Nvidia's largest cloud GPU customers.

This is the core tension in the market. The companies building the most powerful AI are moving to custom silicon for their most demanding workloads. The companies consuming AI are staying on Nvidia for everything else. And the boundary between those two categories is shifting — slowly, then suddenly.

THE BOTTOM LINE

Google has been building the TPU for over a decade. It took eleven years to get from Jeff Dean's napkin calculation about voice search to a chip program projecting 35 million annual shipments by 2028, a $40 billion anchor customer commitment from Anthropic, and the most ambitious architectural bifurcation in custom silicon history.

The eighth-generation announcement at Cloud Next 2026 is not a product launch. It is a declaration. Google is saying that general-purpose silicon is a fading category. That training and inference are irreconcilably different problems that require irreconcilably different hardware. And that the company that has been building specialized silicon since 2015 — the company that literally invented the Transformer architecture that made modern AI possible — is uniquely positioned to solve both.

Whether that declaration proves correct will be determined by a software ecosystem battle that has only just begun, a supply chain that is already straining to serve both internal researchers and billion-dollar external customers, and a manufacturing partnership with TSMC that is the most constrained in semiconductor history.

But the trajectory is unmistakable. The oldest challenger in the AI chip war has arrived. And it brought eight generations of institutional knowledge to the fight.

Next: The rest of the field — Meta's MTIA, Microsoft's Maia, AMD's MI450X, and the startups building the chips that might beat them all. The coalition is larger than anyone has mapped.

— Nicholas Thomas | TrendyVest.com | June 26, 2026

Sources: Google Cloud Blog — Ironwood: The First Google TPU for the Age of Inference · Google Cloud Blog — Eighth Generation TPUs: Two Chips for the Agentic Era · Google Cloud Documentation — TPU7x (Ironwood) Official Specifications · Google Cloud Blog — TPU 8t and TPU 8i Technical Deep Dive · Google Cloud Blog — TPU Transformation: 10 Years of AI-Specialized Chips · Tom's Hardware — Google Deploys Axion CPUs and Ironwood TPU · Tom's Hardware — Inside Google's TPU V8 Strategy · The Register — Google Dual Tracks TPU 8 · Data Center Dynamics — Google Eighth Generation TPUs · The Next Web — Google Ironwood TPU Inference Cloud Next · Tech-Insider — Google TPU 8t and 8i: 121 Exaflops · Hyperframe Research — Google Cloud Next 2026: Bifurcated AI Future · Google Codelabs — Architecting the Agentic Era: TPU 7x, 8t, 8i Analysis · SemiAnalysis — TPUv7: The 900lb Gorilla in the Room · Wikipedia — Tensor Processing Unit · Introl Blog — Google TPU Architecture: 7 Generations Explained · Introl Blog — Google TPU vs Nvidia GPU · Uncoveralpha — The Chip Made for the AI Inference Era · Metaintro — Google's 2026 TPU Squeeze · Hashrateindex — Inside the Custom AI Chip Race · Finomics Edge — Google's Secret Chip · Jeff Dean Google Research Page · Dataknobs — Google TPUs vs Nvidia AMD GPUs 2026